AR# 41169


MIG 7 Series Solution Center - Design Assistant - DDR3 SDRAM - Calculating Efficiency and Effective Bandwidth


To calculate the overall SDRAM performance, peak bandwidth and efficiency must be taken into account.Near peak bandwidth only occurs during bursts of reads or writes. Overhead always exists on the DRAM data bus which lowers the effective data rate.Examples of overhead on the DRAM data bus are:
  • Activate time for new banks/rows
  • Precharge time for changing rows within the same bank
  • Write recovery time to change to read accesses
  • Bus turnaround time to change from read to write
  • Refresh time
  • ZQ Calibration time (DDR3 only)
The amount of overhead varies greatly based on the traffic pattern. Both the command and address patterns are important to analyze. For the command pattern, grouping reads together and writes together results in the least amount of overhead. Whereas, requesting alternating write and read commands (W-R-W-R) results in high overhead to account for Write Recovery Time and bus turnaround time. Similarly, the address pattern can greatly affect the overhead. Sequentially bursting across a row has little to no overhead. Whereas, a random address pattern results in high overhead due to Activate and Precharge times. Consequently, simulating the target traffic pattern must be completed to calculate efficiency.

To properly include any overhead into the overall SDRAM performance, the following should be used to calculate the efficiency and effective bandwidth:
  • Efficiency (%) = Number of Clock Cycles Transferring Data / Total Number of Clock Cycles
  • Effective Bandwidth = Peak Bandwidth * Efficiency

Note: Some users have separate efficiency targets for writes versus reads. Efficiency rates can be calculated separately for reads and writes.

Note:This Answer Record is part of the Xilinx MIG Solution Center(Xilinx Answer 34243)The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


To calculate efficiency, run a simulation with the target traffic pattern driving the user interface of the MIG design and count the number of clock cycles transferring data on the DDR bus and the total number of clock cycles:

  1. Wait for init_calib_complete to assert
  2. Look for the first Activate command associated with the target traffic pattern
  3. Begin counting CK clock cycles - cycle_count
  4. Separately count CK clock cycles where read/write data is being transferred - command_count
  5. Use the numbers found in simulation to calculate efficiency and effective bandwidth per the equations above (efficiency = command_count/cycle_count)

For information on the reordering controller and modifications that might improve efficiency with your traffic pattern, see (Xilinx Answer 36719)

Additional Information
(Xilinx Answer 41054) MIG 7 SeriesDDR3/DDR2 - How does the memory controller send a Read/Write with Auto-Precharge request to the PHY?

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34243 Xilinx Memory Interface Solution Center N/A N/A
51705 MIG 7 Series Solution Center - Design Assistant - Performance N/A N/A

Child Answer Records

Associated Answer Records

AR# 41169
Date 03/04/2013
Status Active
Type Solution Center
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