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AR# 41193

Design Assistant for PCI Express - Link Up Problems


This answer record identifies starting points when debugging hardware related issues to PCI Express.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536) TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.


If you are having link up problems, first step through (Xilinx Answer 34151) Even though this answer is currently targeted to Virtex-6, it can be applied to the 7 Series and Spartan-6 Integrated Block wrappers also.

After going through the debug flow in (Xilinx Answer 34151) if you are still having link up problems, the next step is to determine more about when the failure happens. The easiest way to get this information would be to use a link analyzer if one is available. If not, ChipScope tool can assist in capturing the link training sequence. In many cases, the link will be established but once data begins to flow continual CRC failures on the DLLP or TLP packets will force the link into RECOVERY. This happens so fast thatthe user may think the link is not being established, when in fact it is but then failing. Most of the time these types of failures are due to signal integrity or powering issues on the board.

Revision History

03/10/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34151 Design Assistant for PCI Express - Virtex-6 FPGA Integrated Block for PCI Express Link Up Debugging Diagram N/A N/A
AR# 41193
Date 02/11/2013
Status Active
Type General Article
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )