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AR# 41221

13.1 FPGA Editor - Running a script in FPGA Edline leads to Bitgen DRC errors


Running an FPGA Editor script (.scr file) in FPGA Edline (the command line version of FPGA Editor) leads to DRC errors during BitGen that do not occur when running the script inside the FPGA Editor GUI.  

The errors are similar to the following:

ERROR:PhysDesignRules:1710 - Incomplete connectivity. The pin <ABC> of comp block <DEF> is used and partially connected to network <XYZ>. All networks must have complete connectivity to the comp hierarchy and the connectivity for this pin must be removed or completed.


This occurs when the script changes an attribute of a component in FPGA Editor.  

When using the FPGA Editor GUI a TRIM command will be executed on the component during the block save.

However this command does not happen in FPGA Edline and will not get recorded into any scripts created by FPGA Editor.  

To resolve the issue you need to add a TRIM command on any components for which your script changes any attributes.

For example:

trim -id comp <comp_name>

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
41222 13.1 FPGA Editor - How to automate changes in FPGA Editor using a script N/A N/A
AR# 41221
Date 08/28/2014
Status Active
Type Known Issues
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