Running an FPGA Editor script (.scr file) in FPGA Edline (the command line version of FPGA Editor) leads to DRC errors during BitGen that do not occur when running the script inside the FPGA Editor GUI.
The errors are similar to the following:
This occurs when the script changes an attribute of a component in FPGA Editor.
When using the FPGA Editor GUI a TRIM command will be executed on the component during the block save.
However this command does not happen in FPGA Edline and will not get recorded into any scripts created by FPGA Editor.
To resolve the issue you need to add a TRIM command on any components for which your script changes any attributes.
trim -id comp <comp_name>