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AR# 41227

MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2

Description

The MIG 7 Series Release Notes and Known Issues have been combined into a single answer record for ease of viewing. Please visit (Xilinx Answer 45195).

This Release Note and Known Issues Answer Record is for the Memory Interface Generator (MIG) 7 Series 1.2 released in ISE Design Suite 13.2 and contains the following information:

  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see theIP Release Notes Guide (XTP025).

Solution

General Information

For a list of supported memory interfaces and features for 7 Series FPGAs, see:

7 Series FPGAs Memory Interface Solution Data Sheet (DS176)
7 Series FPGAs Memory Interface Solution User Guide (UG586)

For a list of supported frequencies for 7 Series FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the 7 Series Documentation Center.

The MIG tool includes the appropriate frequency range for each specific memory interface configuration.

For information regarding MIG cores for other FPGAs, see the IP Release Notes Guide (XTP025) to locate the appropriate MIG Release Notes and Known Issues Answer Record.

MIG 7 Series v1.2 supports Xilinx Virtex-7 XT/Xilinx Artix-7 devices. In the ISE Design Suite 13.2 release, these devices are Limited Access and license controlled.

Targeting one of these devices in MAP without the required license will result in security messages.

Please see (Xilinx Answer 42660) for further information.

For general design and troubleshooting information on MIG, see (Xilinx Answer 34243) for the Xilinx MIG Solution Center.

Software Requirements
  • ISE Design Suite 13.2
  • 32-bit Windows XP
  • 32-bit Linux Red Hat Enterprise 4.0
  • 64-bit/32-bit Linux Red Hat Enterprise 4.0
  • 64-bit XP professional
  • 32-bit Vista business
  • 64-bit SUSE 10
  • 64-bit/32-bit Linux Red Hat Enterprise 5.0 support
  • 64-bit Windows Vista support
  • 32-bit SUSE 10 support

New Features

  • ISE Design Suite 13.2 software support
  • Support of Kintex-7 Low Voltage and Virtex-7 Low Voltage devices
  • Support of Artix-7 FPGA Devices
  • Support of DDR3 SDRAM RDIMM and SODIMM designs
  • Support of RLDRAM II designs
  • Support of Fixed Pin Out Selection feature for DDR3 SDRAM and QDRII+ SRAM designs.
  • Support of Verify Pin Changes and Update Design feature for DDR3 SDRAM and QDRII+ SRAM designs.
  • Support PHY to Controller Clock Ratio of 2:1 mode for DDR3 SDRAM designs
  • Support of Input Clock Frequency selection for all interfaces.

Resolved Issues

  • (Xilinx Answer 40426) MIG 7 Series v1.1 - Unrequested Reads are seen in simulation immediately after calibration completes
    • CR 590991
  • (Xilinx Answer 40451) MIG 7 Series v1.1 - tIH violations on ODT and CKE are output by the memory simulation model
    • CR 590528
  • (Xilinx Answer 40452) MIG 7 Series v1.1 - Memory interface should not span both High Range (HR) and High Performance (HP) banks
    • CR 588937
  • (Xilinx Answer 40453) MIG 7 Series v1.1 - Can clk_ref_i, sys_rst, and status signals be located in memory banks (Data or Address/Control banks)?
    • CR 583661
  • (Xilinx Answer 42320) MIG v3.7 Virtex-6 and MIG 7 Series v1.1, DDR3 RDIMM - Incorrect Column Address Width
    • CR 611922
  • (Xilinx Answer 40578) MIG 7 Series v1.1 - Fixed latency mode is not supported for QDRII+ designs
    • CR 589118
  • (Xilinx Answer 40579) MIG 7 Series v1.1 - During re-customization of QDRII+ designs, the bank selection page fails to remember the previous bank selection
    • CR 590052
  • (Xilinx Answer 40580) MIG 7 Series v1.1 - SBG324 and FBG484 packages do not have enough banks to fit x36 QDRII+ parts
    • CR 589785
  • (Xilinx Answer 40871) MIG 7 Series v1.1 - The minimum frequency for QDRII+ designs is 200 MHz
    • CR 593577, CR 593921
Known Issues

(Xilinx Answer 42665) MIG 7 Series v1.2 - Why does the MIG Example Design fail in BitGen?
(Xilinx Answer 42836) MIG 7 Series v1.2 - Incorrect PHASER IN and PHASER OUT constraints generated for compatible Artix-7 device
(Xilinx Answer 42678)13.2 BitGen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"
(Xilinx Answer 42811) MIG 7 Series v1.2 - Setup error on PHY Hard blocks due to incorrect timing model
(Xilinx Answer 42808) MIG 7 Series v1.2 - Component Switching Limit Error on PHY Hard blocks due to incorrect timing model.
(Xilinx Answer 42831) MIG 7 Series v1.2 DDR3/QDRII+/RLDRAM II - design fails in core generation with single-ended system clock
(Xilinx Answer 43250) MIG 7 Series v1.1-v1.2 DDR3/DDR2 - Internal VREF constraint is not applied across all memory banks
(Xilinx Answer 44019) MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL = "OFF" is supported for hardware only and not behavioral simulation
(Xilinx Answer 43908) MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL" option is not documented in UG586

DDR3 SDRAM Memory Interface Designs

(Xilinx Answer 42832) MIG 7 Series v1.2 DDR3 - FULL calibration mode violates tREFI requirement
(Xilinx Answer 42833) MIG 7 Series v1.2 DDR3 - Parity error for RDIMM designs during memory initialization and calibration process
(Xilinx Answer 42834) MIG 7 Series v1.2 DDR3 - tIH and tIS violation on CKE and ODT pins for DDR3 SDRAM designs during simulation
(Xilinx Answer 41981) MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Addr/Ctrl pins should be limited to a single bank
(Xilinx Answer 42559) MIG 7 Series v1.1-v1.2 DDR3 SDRAM - additional hard block constraints are incorrectly generated when the reset_n pin is moved to a different bank for a multi-controller design.
(Xilinx Answer 42036) MIG 7 Series v1.1-v1.2 DDR3 - Internal/External VREF Guidelines
(Xilinx Answer 44527) MIG 7 Series v1.2 DDR3 - Minimum Vccint of 1.0V requirement to achieve 1600 Mbps performance

RLDRAM II Memory Interface Designs

(Xilinx Answer 42725)MIG 7 Series v1.2 - No CC pair available for System Clock

QDRII+ SRAM Memory Interface Designs

(Xilinx Answer 42726) MIG 7 Series v1.1-v1.2 QDRII+ - Model name is incorrect in sim.do for Cypress x36 component
(Xilinx Answer 42729) MIG 7 Series v1.1-v1.2 QDRII+ - Custom x36 memory part showing the wrong data width
(Xilinx Answer 42730) MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in ".veo"

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44527 MIG 7 Series v1.2 DDR3 - Minimum Vccint of 1.0V requirement to achieve 1600 Mbps performance N/A N/A
44019 MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL = "OFF" is supported for hardware only and not behavioral simulation N/A N/A
43908 MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL options Not Documented in UG586 N/A N/A
43250 MIG 7 Series v1.1-v1.2 DDR3/DDR2 - Internal VREF Constraint is not Applied Across All Memory Banks N/A N/A
42832 MIG 7 Series v1.2-v1.4 DDR3 - FULL calibration mode violates tREFI requirement N/A N/A
42730 MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in .veo instantiation file N/A N/A
42729 MIG 7 Series v1.1-v1.2 QDRII+ - custom x36 memory part showing the wrong data width N/A N/A
42726 MIG 7 Series v1.1-v1.2 QDRII+ - Model name is incorrect in sim.do for Cypress x36 component N/A N/A
42725 MIG 7 Series v1.2 - No CC pair available for System Clock N/A N/A
42678 13.2 Bitgen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" N/A N/A
42665 MIG 7 Series - Why does the MIG Example Design fail in BitGen? N/A N/A
42660 13.2/13.3 ISE Design Suite Known Issues - Limited Access for Artix-7 and Virtex-7 XT Devices N/A N/A
42036 MIG 7 Series - Internal/External VREF Guidelines N/A N/A
42559 MIG 7 Series v1.1, v1.2 DDR3 SDRAM - Additional hard block constraints are incorrectly generated when reset_n pin is moved to a different bank for a multi-controller design N/A N/A
43347 Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record N/A N/A
42831 MIG 7 Series DDR3/QDRII+/RLDRAM II - Design Fails in Core Generation with Single-ended System Clock N/A N/A
AR# 41227
Date Created 06/24/2011
Last Updated 08/12/2014
Status Active
Type Release Notes
Devices
  • Kintex-7
  • Virtex-7
  • Artix-7
Tools
  • ISE Design Suite - 13.2
IP
  • MIG