Description

This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.8 released in ISE Design Suite 13.2 and contains the following information:

• General Information  
• Software Requirements 
• New Features  
• Resolved Issues 
• Known Issues  

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

MIG v3.8 is available through ISE Design Suite 13.2.

For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the following user guides:

Spartan-6 FPGA Memory Controller User Guide (UG388)
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf

Memory Interface Solutions User Guide (UG416)
http://www.xilinx.com/support/documentation/ip_documentation/ug416.pdf

For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the following documentation:

Virtex-6 FPGA Memory Interface Solutions User Guide (UG406)
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

Virtex-6 FPGA Memory Interface Solutions Data Sheet (DS186)
http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf

For general design and troubleshooting information on MIG, see (Xilinx Answer 34243) for the Xilinx MIG Solution Center.

Software Requirements

• Xilinx ISE Design Suite 13.2
• 32-bit/64-bit Windows XP Professional
• 32-bit/64-bit Windows 7 Professional
• 32-bit/64-bit Windows Server 2008
• 32-bit/64-bit Linux Red Hat Enterprise 4.0
• 32-bit/64-bit Linux Red Hat Enterprise 5.0
• 32-bit/64-bit SUSE Linux Enterprise 11

New Features

• ISE Design Suite 13.2 software support

Resolved Issues

MIG User Guide

• DS186: Update notes as only behavioral simulation is supported
  • CR 602959

MIG Tool

• Fixed issue with HXT banks numbering in "Verify UCF and Update Design and UCF" feature.
  • CR 602186

Virtex-6 FPGA

• Fixed issues with state machine in axi wrapper module.
  • CR 609407
• Updated the column address width as proper value for certain DDR3 SDRAM RDIMMs.
  • CR 604039
• Phy Latency value is limited to a minimum value of 16 for both QDRII+ SRAM and RLDRAM II interfaces.
  • CR 595149
• Added support for 144 data width for MT9HTF12872CHY-667 device.
  • CR 594386
• Fixed warning issue in controller for Row Address width of 13 for DDR3 SDRAM and DDR2 SDRAM interfaces.
  • CR 592399
• Changed the signals tb_clk/clk_tb to ui_clk and rst_clk_tb/tb_rst to ui_clk_sync_rst in user design top module.
  • CR 580833
• (Xilinx Answer 41608) MIG v3.7 Virtex-6 DDR3 - "app_wdf_wren" stays low even though the write data FIFO should be ready
  • CR 604796
• (Xilinx Answer 40741) MIG v3.61-v3.7 Virtex-6 QDRII+ - "WARNING:PhysDesignRules:2282 - Invalid configuration (incorrect pin connections and/or modes) on block..."
  
  • CR 594189
• (Xilinx Answer 37863) MIG v3.6-v3.7, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error
  
  • CR 572670
• (Xilinx Answer 38104) MIG v3.6-v3.7, Virtex-6 DDR3 - GUI does not allow AXI RDIMM data width selection
  
  • CR 570968
• (Xilinx Answer 40468) MIG v3.7 Virtex-6 AXI - Verify UCF and Update Design and UCF does not work properly with MIG v3.61 designs.
  
  • CR 592681
• (Xilinx Answer 41768) MIG v3.7 Virtex-6 DDR2/DDR3 - AXI simulations fail during compilation when using ISE Simulator
  
  • CR 595314
• (Xilinx Answer 42195) MIG v3.7 Virtex-6 DDR2/DDR3 - For ECC enabled designs, app_correct_en is not driven properly and ECC is not working
  
  • CR 601918
• (Xilinx Answer 42198) MIG v3.7 Virtex-6 DDR2/DDR3 - For ECC enabled designs, app_wdf_mask is not driven properly
  
  • CR 608301
• (Xilinx Answer 42320) MIG Virtex-6 and MIG 7 Series v1.1, DDR3 RDIMM - Incorrect Column Address Width
  
  • CR 611922
• (Xilinx Answer 41444) MIG v3.61-v3.7 Virtex-6 HXT DDR2/DDR3 - BUFR / RSYNC / IODELAY column constraints
  
  • CR 602186
• (Xilinx Answer 41965) MIG v3.7 Virtex-6 DDR2/DDR3 - HAMMER data pattern does not work in simulation
  
  • CR 607735

Spartan-6 FPGA

• Soft Calibration state machine always is always referred as one-hot encoding and fixed this issue by modifying the RTL code.
  • CR 604483
• Calibrated input termination is modified to support different PNSKEW for DQSn and DQSp.
  • CR 591662
• Updated the reset logic as synchronous to fix the timing issues for certain configurations.
  • CR 590316
• Added support for new memory parts for DDR3 SDRAM and DDR2 SDRAM.
  • CR 576843
• Provided TIG constraints for LPDDR in comments for self refresh mode to fix the timing issues.
  • CR 576425
• (Xilinx Answer 38696) Spartan-6 - Use of FPGA Suspend Mode and Self-Refresh Resets MCB
  • CR579077
• (Xilinx Answer 42780) MIG 3.7 Spartan-6 MCB - Failure in NGDBUILD due to improper TIG in constraints file
  • CR608760
• (Xilinx Answer 40385) MIG Spartan-6 MCB - Timing violation on clock domain crossing when user interface clock and calibration clock have an odd ratio
  • CR605293
• (Xilinx Answer 40557) MIG v3.7 Spartan-6 MCB - Multi-controller example designs might not connect up all user logic clocks
  • CR604771

Known Issues

Virtex-6 FPGA MIG Designs

(Xilinx Answer 38731) MIG v3.5-v3.8, Virtex-6 DDR3 - Simulation - 'SKIP' calibration causes errors in the Example Design
(Xilinx Answer 41653) MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator address data masking is inconsistent in cmd_gen.vhd
(Xilinx Answer 39423) MIG v3.6-v3.8 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/O's which require another bank for DCI Cascade
(Xilinx Answer 42233) MIG v3.7-v3.8 Virtex-6 RLDRAM II - Address Width does not change when using Address Multiplexing
(Xilinx Answer 41918) MIG v3.7-v3.8 Virtex-6 DDR2/DDR3 - Traffic Generator does not simulate other data or command patterns
(Xilinx Answer 41652) MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator error_status does not latch correct data
(Xilinx Answer 35750) MIG v3.4-v3.8 Virtex-6 QDRII+ - Why is the QVLD signal left unconnected?
(Xilinx Answer 42827) MIG v3.8 Virtex-6 QDRII+ - ChipScope cores are not detected in the JTAG device chain

Spartan-6 FPGA

(Xilinx Answer 36550) MIG v3.5, Spartan-6 MCB - Synplify fails on a MIG output design with error "port LOCKED does not exist"
(Xilinx Answer 38000) MIG v3.6 Spartan-6 MCB - WARNING:sim - ProjectMgmt - Circular Reference: work:Module|mux
(Xilinx Answer 38651) MIG 3.6 Spartan-6 - DDR termination recommendation
(Xilinx Answer 38524) MIG Spartan-6 - Debug signals are only added to first port in the user interface
(Xilinx Answer 38623) MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps?
(Xilinx Answer 40311) MIG v3.7 Virtex-6, Spartan-6 - UCF changes to support Synplify E-2010.09-1-SP2
(Xilinx Answer 42828) MIG 3.8 Spartan-6 MCB - Some AXI simulations are failing due to simulator memory overflow
(Xilinx Answer 42829) MIG 3.8 Spartan-6 MCB - Custom part for MCB allows ranges that exceed supported address space

Linked Answer Records

Child Answer Records

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