This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.8 released in ISE Design Suite 13.2 and contains the following information:
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
General Information
MIG v3.8 is available through ISE Design Suite 13.2.
For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the following user guides:
Spartan-6 FPGA Memory Controller User Guide (UG388)
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
Memory Interface Solutions User Guide (UG416)
http://www.xilinx.com/support/documentation/ip_documentation/ug416.pdf
For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the following documentation:
Virtex-6 FPGA Memory Interface Solutions User Guide (UG406)
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf
Virtex-6 FPGA Memory Interface Solutions Data Sheet (DS186)
http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf
For general design and troubleshooting information on MIG, see (Xilinx Answer 34243) for the Xilinx MIG Solution Center.
Software Requirements
New Features
Resolved Issues
MIG User Guide
MIG Tool
Virtex-6 FPGA
Spartan-6 FPGA
Known Issues
Virtex-6 FPGA MIG Designs
(Xilinx Answer 38731) MIG v3.5-v3.8, Virtex-6 DDR3 - Simulation - 'SKIP' calibration causes errors in the Example Design
(Xilinx Answer 41653) MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator address data masking is inconsistent in cmd_gen.vhd
(Xilinx Answer 39423) MIG v3.6-v3.8 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/O's which require another bank for DCI Cascade
(Xilinx Answer 42233) MIG v3.7-v3.8 Virtex-6 RLDRAM II - Address Width does not change when using Address Multiplexing
(Xilinx Answer 41918) MIG v3.7-v3.8 Virtex-6 DDR2/DDR3 - Traffic Generator does not simulate other data or command patterns
(Xilinx Answer 41652) MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator error_status does not latch correct data
(Xilinx Answer 35750) MIG v3.4-v3.8 Virtex-6 QDRII+ - Why is the QVLD signal left unconnected?
(Xilinx Answer 42827) MIG v3.8 Virtex-6 QDRII+ - ChipScope cores are not detected in the JTAG device chain
Spartan-6 FPGA
(Xilinx Answer 36550) MIG v3.5, Spartan-6 MCB - Synplify fails on a MIG output design with error "port LOCKED does not exist"
(Xilinx Answer 38000) MIG v3.6 Spartan-6 MCB - WARNING:sim - ProjectMgmt - Circular Reference: work:Module|mux
(Xilinx Answer 38651) MIG 3.6 Spartan-6 - DDR termination recommendation
(Xilinx Answer 38524) MIG Spartan-6 - Debug signals are only added to first port in the user interface
(Xilinx Answer 38623) MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps?
(Xilinx Answer 40311) MIG v3.7 Virtex-6, Spartan-6 - UCF changes to support Synplify E-2010.09-1-SP2
(Xilinx Answer 42828) MIG 3.8 Spartan-6 MCB - Some AXI simulations are failing due to simulator memory overflow
(Xilinx Answer 42829) MIG 3.8 Spartan-6 MCB - Custom part for MCB allows ranges that exceed supported address space
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
42827 | MIG v3.8 Virtex-6 QDRII+ - ChipScope cores are not detected in the JTAG device chain | N/A | N/A |