AR# 41408


7 Series - How to place LVDS in a High Performance bank


In 7 Series FPGAs there are a mixture of High Performance (HP) and High Range (HR) banks. An HP bank has a maximum Vcco of 1.8V.

How do you define LVDS for an HP bank?


The IOSTANDARD for an HR bank is LVDS_25 and the IOSTANDARD for an HP is LVDS.

Both LVDS and LVDS_25 are documented in the 7 Series FPGAs SelectIO User Guide (UG471).

LVDS inputs are supported on an HP bank powered at Vcco=1.5V, but the swing should be limited to meet the Vin specification of Vcco + 0.2V.

Note: If the swing is 1.725V or below this will not cause issues. The internal DIFF_TERM is not supported on banks powered at 1.5V; therefore, an external 100 ohm differential termination resistor is required.

For information on voltage compatibility between LVDS in HP and HR banks, see (Xilinx Answer 40191)

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40191 7 Series - LVDS compatibility between 1.8V LVDS and 2.5V LVDS signals N/A N/A
AR# 41408
Date 09/04/2017
Status Active
Type General Article
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