The IOSTANDARD for an HR bank is LVDS_25 and the IOSTANDARD for an HP is LVDS.
Both LVDS and LVDS_25 are documented in the 7 Series FPGAs SelectIO User Guide (UG471).
LVDS inputs are supported on an HP bank powered at Vcco=1.5V, but the swing should be limited to meet the Vin specification of Vcco + 0.2V.
Note: If the swing is 1.725V or below this will not cause issues. The internal DIFF_TERM is not supported on banks powered at 1.5V; therefore, an external 100 ohm differential termination resistor is required.
For information on voltage compatibility between LVDS in HP and HR banks, see (Xilinx Answer 40191)