We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4142

Orcad: Adding third-party Xilinx cores to an Express project


Keywords: third-party, cores, Orcad, Express, project

Urgency: Standard

General description: How to use a Xilinx core generated with a third-party
tool within an Express project?


Express includes schematic symbols and models for all Xilinx Unified
Library macros and can automatically generate library resources for
any LogiBLOX component.

Intellectual property (IP) cores which were created by third-party
EDA systems can also be added to your Express design using the
procedure below:

1.Save the IP core files (usually in the form of an XNF or EDIF
format netlist) in your project.\timed subdirectory. The IP core
files merge with your design logic during the place-and-route phase.

2.Create a schematic symbol (a primitive hierarchical block or
library part) from the IP core file. See the Generate Part on-line
help topic for more information on creating parts from XNF or EDIF
format netlists.

3.Place the part or block in the schematic and add the Xilinx User
Property FILE= to it. Specify the IP core filename as the value of
the FILE= property. See the Xilinx on-line help topic for more
information on Xilinx design attributes.

4.Create a VHDL model of the IP core part to serve as a black box.
The model provides an entity interface only--no architecture is
required. Add the model file as a VHDL Source into the Design
Resources folder of the project.

Note: A quick way to create this model is to specify the
implementation type as being VHDL for the schematic part or
block. Descend the hierarchy to create a new model and
automatically add the model file as a design resource.

5.Implement the project using the Express Compile and Build tools.

Tips for simulation of XNF format IP cores:

If the file format is XNF, you may want to perform a functional
simulation to confirm the design logic.

Express can convert the output of the XACTstep programs (such as
XNFMerge (.XFF), or XBLOX (.XG)) into a simulation model for
functional simulation. See "Convert XNF to VHDL" in the Orcad on-line
help for more information.

AR# 4142
Date 10/06/2008
Status Archive
Type General Article