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AR# 41495

MIG Virtex-6 DDR2/DDR3 - Design information on ECC


This answer record includes more detailed information on the Virtex-6 DDR2/DDR3 design's ECC logic.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Description of ECC_TEST:

If ECC_TEST is set to "ON", then the entire DRAM bus width carries through the UI. For example, if theDATA_WIDTH == 64, then the app_rd_data width is 288.

When ECC_TEST is set to"ON", the entire DRAM read data is available on app_rd_data. For writes, four more control bits areimplemented. The control bits determine whether the computed ECC, or the extra bits supplied on app_wdf_data are written to the DRAM in the ECC bit positions.

ECC Signals:

App_correct_en disables the bit flips only.It does not disable the error indication signals. This allows errors to be seeded and observed independently of thecorrection operations.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34316 MIG Virtex-6 DDR2/DDR3 - Supported Features N/A N/A
AR# 41495
Date 01/31/2013
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
  • Virtex-6 SXT
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  • MIG
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