We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41517

MIG Virtex-6 QDRII+ - MIG V6 QDRII+ - CQ/CQ# Tap Values are maxed out, but calibration still passes with no data errors


During calibration my CA/CQ# Tap Values are maxed out at 1F, but I amnot seeing data errors. Why are the tap values maxed out and should this be a concern?


One reason for the maxed out tap delay values is that calibration is looking for the rise clock to align within the rise window, but it ispossible that there areinternal delays that happen to push the clk into the fall window.In this case,the clock will be delayed until it lands inside the next successive rise window, which is possible since the clk is free running.

This should not be a concern since calibration can delay both the CQ clocks and also delay the data through the use of IODELAYs during Read Stage 1 Calibration, so CQ should still be center aligned near the middle of the valid data window.
AR# 41517
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • More
  • Virtex-6 HXT
  • Virtex-6 SXT
  • Less
  • MIG