We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 41608

MIG v3.7 Virtex-6 DDR3 - "app_wdf_wren" stays low even though the write data FIFO should be ready


During simulation I see "app_wdf_wren" staying low for some period of time. Why does this occurwhen the write data FIFO should be ready to receive data?


Sometimes, this occurs when the "occ_cnt" value counts incorrectly in "ui_wr_data.vhd."

VHDL Users

Change the following line in "ui_wr_data.vhd" from:

wr_data_end <= app_wdf_end_r1 AND app_wdf_rdy_r_copy1;

to include "app_wdf_wren_r1":

wr_data_end <= app_wdf_end_r1 AND app_wdf_rdy_r_copy1 AND app_wdf_wren_r1;

Verilog Users

Change the following line from:

wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1;


wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;

The "wr_data_end" indirectly affects the "occ_cnt" value, which in turn affects the wr_data_index and wr_data_addr and can cause problems in hardware and simulations.

This is fixed in the ISE 13.2 MIG v3.8 release.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 41608
Date 05/20/2012
Status Active
Type Known Issues
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
  • MIG