You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
MIG v3.7 Virtex-6 DDR3 - "app_wdf_wren" stays low even though the write data FIFO should be ready
During simulation I see "app_wdf_wren" staying low for some period of time. Why does this occurwhen the write data FIFO should be ready to receive data?
Sometimes, this occurs when the "occ_cnt" value counts incorrectly in "ui_wr_data.vhd."
Change the following line in "ui_wr_data.vhd" from:
wr_data_end <= app_wdf_end_r1 AND app_wdf_rdy_r_copy1;
to include "app_wdf_wren_r1":
wr_data_end <= app_wdf_end_r1 AND app_wdf_rdy_r_copy1 AND app_wdf_wren_r1;
Change the following line from:
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1;
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
The "wr_data_end" indirectly affects the "occ_cnt" value, which in turn affects the wr_data_index and wr_data_addr and can cause problems in hardware and simulations.
This is fixed in the ISE 13.2 MIG v3.8 release.
Was this Answer Record helpful?
Linked Answer Records
Master Answer Records
- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LX
- Virtex-6 LXT
- Virtex-6 SXT