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  3. AR# 4161: 12.1 Timing - I cannot create a TIMESPEC that includes the TDO/MD1 pin on FPGA architectures

AR# 4161

12.1 Timing - I cannot create a TIMESPEC that includes the TDO/MD1 pin on FPGA architectures

Description

I cannot create TIMESPECs that include the TDO/MD1 output pad on Xilinx FPGAs. When I apply time constraints that directly feed the TDO pin, the timing report indicates the following: 

"0 items analyzed, 0 timing errors detected."

Solution

You can trace the delay to the IOB pin, but you cannot determine the delay in the IOB. This can be done in Timing Analyzer by using the path filters to select the appropriate source and destination. (The destination is the net driving the buffer connected to the TDO.)
AR# 4161
Date 05/14/2014
Status Archive
Type Known Issues
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