Usage Wizard Simulation Silicon Revision Specific Software Protocol Specific(Xilinx Answer 62616) 7 Series GTX/GTH Transceivers: RXCDR_CFG setting for 8B10B unscrambled data at line rates > 6.6 Gbps (Xilinx Answer 60024) Installing In-System Eye Scan in a 7 Series GTX Design (Xilinx Answer 60697) Can userclk and userclk2 be connected to different buffers? (Xilinx Answer 53788) 7 Series DRP port access in GT serial transceivers (Xilinx Answer 53107) 7 Series GTX Transceivers Recommended usage in Near End PCS loopback mode (Xilinx Answer 53500) Serial Transceiver Why is GREFCLK not recommended as REFCLK for GTX? (Xilinx Answer 56894) 7 Series GTX/GTH/GTP Transceivers DFE/LPM Optimized Settings for Non-scrambled Signal (Xilinx Answer 50267) 7 Series GTX/GTH DFE/LPM default settings for 8b10b enabled protocol should be changed (Xilinx Answer 47157) 7 Series FPGA GTX/GTH Transceivers Correct Settings to Enable Digital Monitor (Xilinx Answer 54140) 7 Series Transceivers What are the termination values of transceiver ports before the device is configured? (Xilinx Answer 50468) 7 Series GTX Minimum Pulse Width on DLYSRESETDONE and PHALIGNDONE for Buffer Bypass Auto Mode (Xilinx Answer 51825) Usage of CTLE Auto Adapting Mode in 7 Series GTX (Xilinx Answer 42662) 7 Series GTX Transceiver TX and RX Latency Values (Xilinx Answer 46490) 7 Series GTH Transceiver TX and RX Latency Values (Xilinx Answer 52431) Virtex-7 FPGA GTH Transceivers ACJTAG Use Mode in Engineering Sample (ES) Silicon (Xilinx Answer 52844) 7 Series GTX GTH Production Silicon Correct setup when OOB is not used (Xilinx Answer 45148) 7 Series GTX/GTH CTLE and DFE frozen setup (Xilinx Answer 46024) 7 Series GTX How do you override the Phase Interpolator (PI) phase? (Xilinx Answer 52744) Virtex-7 FPGA GTH Transceivers: Power Supply Grouping Per Package (Xilinx Answer 52668) Virtex-7 FPGA GTX/GTH Transceivers: Multi-lane buffer bypass not supported across SLR boundary (Xilinx Answer 44549) 7 Series FPGA GTX/GTH/GTP Transceivers Reference clock phase noise masks (Xilinx Answer 44587) 7 Series GTX/GTH/GTP Transceivers: RX OOB use modes (Xilinx Answer 47443) Design Advisory for 7 Series FPGAs GTH Transceiver Power-Up/Power-Down (Xilinx Answer 47817) Design Advisory for the Kintex-7 and Virtex-7 GTX Transceiver Power-Up/Power-Down (Xilinx Answer 47342) Design Advisory for Virtex-7 GTH Serial Transceiver Package Diagram corrections (Xilinx Answer 47307) 7 Series FPGA Transceivers How to connect the receiver pins MGTRXP/N when RX not used? (Xilinx Answer 41451) 7 Series GTX Transceivers -What to connect the MGTVCCAUX to if QPLL is unused? (Xilinx Answer 43260) 7 Series GTX Transceivers -RXSLIDE feature in PMA mode not supported with RX buffer bypass (Xilinx Answer 43482) 7 Series GTX Transceivers -Reset requirements upon configuration (Xilinx Answer 43420) Xilinx Serial Transceivers Can the LVDS standard be used for reference clocks? (Xilinx Answer 45598) 7 Series FPGA GTX/GTH Transceivers -Quad Usage Priority Information (Xilinx Answer 46200) 7 Series GTP/GTX/GTH RXBYTEISALIGNED is not always reliable (Xilinx Answer 47331) 7 Series FPGA GTX/GTH Transceivers No Power Sequencing Requirement for MGTAVTT/MGTVCCAUX (Xilinx Answer 43641) MGT Does GTX/GTP/GTH support REFCLKs with HCSL I/O standard? (Xilinx Answer 56066) 7 Series FPGAs GTX/GTH/GTP Transceivers: Optimal RX Buffer Settings CLK_COR_MIN_LAT and CLK_COR_MAX_LAT (Xilinx Answer 54691) IP Release Notes and Known Issues for 7 Series FPGAs Transceivers Wizard for Vivado 2013.1 and newer versions (Xilinx Answer 63817) 7 Series FPGAs Transceivers Wizard Example Design v3.5Use of clocking resources to check for tx|rxoutclk (Xilinx Answer 63110) Design Advisory for 7 Series GTH Transceiver Wizard: DFE incorrectly set to HOLD after adaptation in Vivado 2013.4 to 2014.4 (Xilinx Answer 61875) Design Advisory for QPLL based 7 Series FPGA GTX/GTH designs: QPLLPD should not be enabled for min time of 500ns after configuration is complete (Xilinx Answer 59294) Design Advisory GT wizard CPLL causes power spike on power up for 7 series GTs (Xilinx Answer 60356) Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier Required XDC constraint Updates (Xilinx Answer 59612) 7 Series GTX buffer bypass mode: how to correctly set the parameter PCS_RSVD_ATTR (Xilinx Answer 57592) v7ht.tcl file related Warning message while implementing example design using GTX (Xilinx Answer 61303) 7 Series Transceiver Wizard 3.3VHDL errors with selecting 'TX off' (Xilinx Answer 60489) Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier: GTH/GTP Production RX reset sequence can get stuck (Xilinx Answer 61155) 7 Series GTH Wizard v3.2GT Wizard generates wrong attributes (Xilinx Answer 59150) 7 Series FPGA GTX/GTH Transceivers Wizard v3.1Tx Buffer Bypass does not complete successfully in auto mode (Xilinx Answer 58244) Design Advisory for 7 Series FPGA GTX Transceiver RXDFEXYDEN Port Update in DFE Mode (Xilinx Answer 61161) V3.17 Series FPGAs Transceivers Wizard An incorrect GTREFCLK port name may be generated in an example design (Xilinx Answer 61154) v3.17 Series FPGAs Transceivers Wizard simulation fails if both LPM mode and Near-end PMA Loopback are selected at the same time (Xilinx Answer 60488) 7 Series FPGA Transceivers Wizard v3.0: GTX/GTH/GTP reset sequence might not complete successfully with the reset FSM's from the wizard (Xilinx Answer 58608) 7 Series FPGAs Transceivers Wizard Example Design v3.0Use of clocking resources to check for tx|rxoutclk (Xilinx Answer 59184) 7 Series FPGAs GTX/GTH Transceivers Wizard v3.1EXAMPLE_SIMULATION not passed to gtwizard_0_tx_startup_fsm.v (Xilinx Answer 55009) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode (Xilinx Answer 56117) 7 Series GTX/GTH/GTP TX buffer bypass port settings mismatch with user guide (Xilinx Answer 55791) Design Advisory for 7 Series FPGAs Transceivers Wizard Required Updates to Wizard v2.5 (Xilinx Answer 55366) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers: Transceiver Wizard Sets Suboptimal RX Termination Use Modes (Xilinx Answer 53396) 7 Series FPGAs Transceiver Wizard v2.4Known Issues and Release Notes (Xilinx Answer 52868) 7 Series FPGA GTX Transceivers: Line rate/USRCLK limitation for -1 speed grade in 16-bit data path mode (Xilinx Answer 52263) 7 Series FPGAs Transceivers Wizard v2.3Known Issues and Release Notes (Xilinx Answer 50299) 7 Series FPGAs Transceivers Wizard and Aurora 8B10B/64B66B Cores Support for GTX Transceivers in Zynq Devices (Xilinx Answer 50890) 7 Series FPGAs Transceivers Wizard Flow in Vivado Design Suite 2012.2/2012.3/2012.4 (Xilinx Answer 50827) 7 Series FPGAs Transceivers Wizard v2.2Known Issues and Release Notes (Xilinx Answer 47477) 7 Series FPGAs Transceivers Wizard v2.1Known Issues and Release Notes (Xilinx Answer 47304) Aurora 8B10B v8.1/64B66B v7.1 and 7 series Transceiver Wizard How to generate Aurora cores/GT wrappers for XQ7VX690T/TL RF1930 device? (Xilinx Answer 46048) 7 Series FPGAs Transceivers Wizard What silicon revisions are supported by different Wizard or ISE design tool versions? (Xilinx Answer 47054) 7 Series FPGAs Transceivers Wizard User defined comma for SONET not allowed (Xilinx Answer 45685) 7 Series FPGAs Transceivers Wizard v1.6Known Issues and Release Notes (Xilinx Answer 44988) 7 Series FPGAs Transceivers Wizard v1.5Incorrect Internal and External Data Widths with 8B10B (Xilinx Answer 44463) 7 Series FPGAs Transceivers Wizard v1.5Known Issues and Release Notes (Xilinx Answer 42809) 7 Series FPGAs Transceivers Wizard v1.4Known Issues and Release Notes (Xilinx Answer 40748) 7 Series FPGAs Transceivers Wizard v1.3Known Issues and Release Notes (Xilinx Answer 41773) 7 Series GT Wizard Selecting Independent Line Rates in TX and RX (Xilinx Answer 42591) 7 Series FPGA GTX Transceivers TX/RX Buffer Bypass Default Attribute Settings (Xilinx Answer 47492) 7 Series FPGA GTH/GTP Buffer Bypass Default Attribute Settings (Xilinx Answer 60114) Where can I get the 7-series IBIS-AMI models? (Xilinx Answer 61175) Correspondence table between 7-Series GTX IBIS-AMI model and GTX Parameters (Xilinx Answer 63745) IBIS-AMI simulation Kit: what is included in the package Scattering Parameter models (Xilinx Answer 46083) Is there a 64-bit version of the .dll file for the GTX IBIS-AMI models? (Xilinx Answer 44940) 7 Series HSPICE Models (Xilinx Answer 47318) 7 Series FPGA GTH Transceivers Long simulation run times (Xilinx Answer 42842) 7 Series GTX Transceiver PLLREFCLK selection change causing simulation issue in ISE Design Suite 13.1 (Xilinx Answer 47318) 7 Series FPGA GTH Transceivers Long simulation run times (Xilinx Answer 47494) 7 Series GTX IBISAMI Model Advanced Use Mode (Xilinx Answer 51198) 7 Series GTX Fast Simulation Models Speed up of GTXE components for the ISE environment (Xilinx Answer 47171) ModelSim 10.1 problems with Serial Transceivers (Xilinx Answer 43489) Virtex-7, Kintex-7How to correctly setup IBIS-AMI simulation (Xilinx Answer 51714) 7 Series GTXIBIS-AMI model v2.1 Stat model does not support LPM mode simulation (Xilinx Answer 56332) Design Advisory for Virtex-7 GTHQPLL Attribute Updates for Production Silicon (Xilinx Answer 43244) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon (Xilinx Answer 45360) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon (Xilinx Answer 45410) 7 Series FPGA GTX Transceivers Initial ES to General ES Silicon GTX Migration (Xilinx Answer 47128) Design Advisory for the Virtex-7 FPGA GTH Transceiver Attribute Updates and Use Modes for Initial Engineering Sample (ES) Silicon (Xilinx Answer 50617) Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceivers (Xilinx Answer 51625) Design Advisory for the Virtex-7 FPGA GTH Transceiver Attribute Updates and Use Modes for General Engineering Sample (ES) Silicon (Xilinx Answer 51884) Design Advisory for Kintex-7/Virtex-7 GTX Production Silicon CDR Attribute Updates (Xilinx Answer 53779) Design Advisory for Virtex-7 FPGA GTH Transceiver RX Reset Sequence Requirement for Production Silicon (Xilinx Answer 52040) IBERT EyeScan not supported with 20 and 40-bit RX internal data width in 7 series GTH (GES Silicon) (Xilinx Answer 56820) 7 Series GTX Transceiver EyeScan Power Consumption in Production Silicon (Xilinx Answer 43339) 7 Series FPGA GTX Transceiver Software Use Model Changes (Xilinx Answer 63076) CRITICAL WARNING: [Timing 38-282] reported when GT reference clock is set to 820MHz for -1/-2 speed grades (Xilinx Answer 63225) 7 Series GTX/GTH Critical Warning is reported when I attempt to use QPLLOUTREFCLK to drive fabric logic (Xilinx Answer 53920) 7 series GTX placement failed after switching from Virtex-7 to Kintex-7 (Xilinx Answer 63869) 7 Series FPGA GTX/GTH/GTP Transceivers Recommendation on CDR usage for SATA protocol (Xilinx Answer 53364) 7 Series FPGA GTX/GTH Transceivers Recommendations and Settings for SATA Gen 1, Gen 2, Gen 3 Optimal Performance (Xilinx Answer 44788) 7 Series FPGA GTH Transceivers -PCI-Express Receiver Detection Time (Xilinx Answer 59035) Design Advisory for 7 Series FPGA GTX/GTH Transceivers - QPLL not supported for PCIe Gen1/Gen2
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 54480 | LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 44988 | 7 Series FPGAs Transceivers Wizard v1.5 - Incorrect Internal and External Data Widths with 8B10B | N/A | N/A |
| AR# 41613 | |
|---|---|
| Date | 09/05/2018 |
| Status | Active |
| Type | Known Issues |
| Devices |
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| IP |
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