When I generate a bitstream for a 7 Series device, the following error message occurs:
For example, this message applies to the following I/O ports:
The 13.2 BitGen software introduces this change to protect devices from accidental damage that could be caused by the tools randomly choosing a pin location or IOSTANDARD without knowledge of the board voltage or connections.
The default I/O standard for the 7 Series is LVCMOS18 for single-ended signals for all banks, the default I/O standard was LVCMOS25 in previous architectures.
As the message indicates, the error can be downgraded to a warning by setting the -g UnconstrainedPins:Allow switch in either of the following:
However, you must ensure that all the pins are in the appropriate locations. The Pinout Report (.pad) lists the location of the pins after PAR as well as the IOSTANDARD.
If the IOSTANDARD is listed with an asterisk (*), for example, LVCMOS18*, then the IOSTANDARD was undefined by the user and the software used a "default" setting.
You need to ensure that this IOSTANDARD is compatible with the voltages, terminations, and connectivity of the board before down grading the warning.
Note: A "default" IOSTANDARD is applied during Map/Par to provide an output .ncd for the analysis tools (Timing, Power, etc.), however IOSTANDARDs must be specified or BitGen will error out with the above error.
Note: The recommended user flow is to select all IOSTANDARDs and pin placements in the design, for example, the UCF file.
Do not place LVCMOS18 in High Range banks that are powered at 2.5V or 3.3V.
Xilinx IP CoresSome Xilinx IP cores might be affected by this problem when implementing the example design included with the core.
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