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AR# 41706

MIG 7 Series - Can FPGA banks be shared among memory interfaces?

Description

Is it possible to share an FPGA bank between two MIG interfaces?

If a bank containing one memory interface contains unused T* byte groups, can these unused byte groups be assigned to a different memory controller?

Solution

No, FPGA banks cannot be shared between multiple memory controllers. 

Each MIG interface requires a unique PHY Control Block in all interface banks.

The PHY Control Block is dedicated logic that controls the FIFOs and Phasers within the bank.

Both Address/Control and Data Byte Groups use the PHY Control Block within the bank and only one PHY Control Block exists in an FPGA bank.

Therefore, it is not possible to share a bank between two interfaces.

This is documented in the Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide (UG586)


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51317 MIG 7 Series DDR2/DDR3 - Verify pin-out/banking requirements are met N/A N/A
51676 MIG 7 Series Solution DDR2/DDR3 - Supported Features N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
60952 MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
60952 MIG 7 Series - Pinout validation in Fixed Pinout Mode does not check against multiple controllers N/A N/A
AR# 41706
Date Created 08/16/2012
Last Updated 08/13/2014
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
IP
  • MIG