I am inferring a BRAM with independent read and write clock.
When I run bitgen I get the following warning:
INFO:PhysDesignRules:2288 - The read port and write port clocks of BRAM
instance, Mram_mem_data, are using the same clock signal(synchronous
clocking) with WRITE_FIRST mode specified. This configuration may encounter
address collisions if the same address appears on both ports. It is suggested
for this configuration to use READ_FIRST mode to avoid any conditions for
address collision. See the Virtex-6 FPGA Memory Resources User Guide for
Does bitgen or MAP/PAR modify the design and uses the same clock? In the RTL design the BRAM are clocked with the independent clocks iclock and oclock.