AR# 41810
|12.4/13.4/14.7 Map - ERROR:Place:1206 global buffer instance driving the non-clock source pins off chip
Description
I am using 6slx45-2csg324.
The design has input differential clock pads driving one BUFIO2, and the BUFIO2 drives one BUFG.
The BUFG drives one pin off chip directly.
It works correctly with input clock pads located at D11 and C11.
However, it fails when the pads are located at U10 and V10.
The following errors are received:
ERROR:Place:1206 - This design contains a global buffer instance,
<u_isds/clkdiv_buf_inst>, driving the net, <RXCLKA_OBUF>, that is driving the
following (first 30) non-clock source pins off chip.
< PIN: RXCLKA.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue. Although the net
may still not route, you will be able to analyze the failure in FPGA_Editor.
< PIN "u_isds/clkdiv_buf_inst.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1136 - This design contains a global buffer instance,
<u_isds/clkdiv_buf_inst>, driving the net, <RXCLKA_OBUF>, that is driving the
following (first 30) non-clock source pins.
< PIN: RXCLKA.O; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay, skew or unroutable
situations. It is recommended to only use a BUFG resource to drive clock
loads. If you wish to override this recommendation, you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "u_isds/clkdiv_buf_inst.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
Solution
There are limitations on routing BUFG to output directly:1.The top 8 BUFGs will also route to non-clock inputs such as LUTs, .CE and .SR pins but it is not advised to use the BUFGs to route to non-clock loads.
It is very easy to create an unroutable design.
2.The bottom 8 BUFGs will route to clocks and .SR pins only.
There is absolutely no route from a bottom 8 BUFG to a LUT or IOB input or .CE pins.
If you use U10 and V10 as the global clock inputs, according to Figure 1-4 of UG382 (v1.5), it will route to BUFIO2_X1Y6 or BUFIO2_X3Y6.
Eventually, these two BUFIO2's will route to BUFGMUX_X3Y15,BUFGMUX_X3Y16,BUFGMUX_X2Y11 and BUFGMUX_X2Y12, according to Figure 1-4 of UG382 (v1.5).
All of these BUFG's are in the bottom so they are not allowed to route to output pins directly.
One workaround is to use an ODDR to output clock signal instead of using a "clock forwarding" configuration.
| AR# 41810 | |
|---|---|
| Date | 09/11/2014 |
| Status | Active |
| Type | General Article |
| Devices | |
| Tools | |