AR# 4185: FPGA Express: How to disable clock period specification
AR# 4185
FPGA Express: How to disable clock period specification
Description
Keywords: FPGA Express, clock, period
Urgency: Standard
General Description: When exporting timing constraints from FPGA Express, constraints for all valid clocks and paths are written, regardless of whether or not you wish to constrain that path.
How does one disable a clock or path timing specification?
Solution
1
If you do not care about the timing of a certain clock, simply place a very loose timing specification on that clock.
2
With Express 3.2 and newer, all timing constraints are written to an NCF file. This file may be edited by the user, so unwanted constraints can be simply removed from this file.
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AR# 4185
Date
08/11/2003
Status
Archive
Type
General Article
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