When a clock has been placed on local routing, the clock delay can be greater than the input path delay. If an OFFSET constraint is placed on the input in question, TRCE/Timing Analyzer will report a negative OFFSET. (Similar results are sometimes seen with setup and hold times.)
The resolution is to place a TIMESPEC on the CLK net. This will cause the tools to evaluate the delay on the clock line.
TIMESPEC TS01 = FROM PADS(CLK) TO FFS 10ns;
where "CLK" is the net name between the pad and the buffer.
Another solution is to add delay to the data path. You can do this by moving the flip-flop further away from the IOB.