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AR# 41909

Virtex-6 GTH Transceivers - TX and RX Latency Values

Description

This Answer Record contains the TX and RX latency values for the Virtex-6 FPGA GTH Transceiver. This table will be included in a future release of the Virtex-6 FPGA GTH Transceiver User's Guide (UG371).

Solution

Data Mode

Fabric Interface

Data Width

PCS (TX) PCS (RX) PMA (TX) PMA (RX)
min max min max min max min max
UI UI UI UI UI UI UI UI
RAW 16, 32, 64 48 64 48 64 2 2 17 17
RAW 20, 40, 80 60 80 60 80 2 2 21 21
8B10B 16, 32, 64 80 100 80 100 2 2 21 21
64B66B(1) 64 178 226 278 376 2 2 17 17

NOTE:

(1) Rising edge of MAC->PCS clock to bit 0 output onwire for TX; Bit 0 received on wire to time data is available on PCS->MAC for RX.

The table above shows the TX and RX latency values for both PCS and PMA. In addition, there are two FIFOs: TX FIFO and RX FIFO whose latencies need to be considered. The latencies of these FIFOs are as follows:

Block Min (UI) Max (UI)
TX FIFO 1* n(2) 4* n(2)
RX FIFO 1 * n(2) 4 * n(2)

NOTE:

(2) 'n' is the fabric interface data width.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38596 Virtex-6 FPGA GTH Transceiver - Known Issues and Answer Records List N/A N/A
AR# 41909
Date Created 05/06/2011
Last Updated 02/04/2013
Status Active
Type General Article
Devices
  • Virtex-6 HXT