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AR# 42034

Aurora 64b/66b - Reduction of BUFGs in Virtex-5 and Virtex-6 GTX devices


An Aurora 64B/66B core consumessix BUFGs in total for any given design configuration using Virtex-5 or Virtex-6 GTX devices. The increase in usage of BUFGs compared to an Aurora 8b/10b core is due to the fact that Aurora 64B/66B is an 8-byte protocol, while the maximum fabric interface datawidth supported by Virtex-5/Virtex-6 GTX is 4-byte. Clock Correction and Channel Bonding are done in the fabric and run on the recovered clock domain. Especially in designs in which more thanone core is instantiated this can cause for a shortage of BUFGs. Below aretwo guidelines which can save BUFGs in some situations.


The Aurora 64B/66B core generates 3 clocks each on transmit and receive side to clock its logic with respective interface widths.

Following are the guidelines to reduce the BUFG usage of the core:
  • If the line rate is same across all cores(for multiple cores) without PPM variation in clock, then the same clocks can be used to clock the cores
  • Some cores can be grouped to reduce the fanout load on the clock nets
  • Use BUFRs in places of BUFGs
  • The UCF needs to be updated with the respective constraint for the BUFR location
AR# 42034
Date 12/15/2012
Status Active
Type General Article
  • Aurora 64B/66B