The 7 series FPGAs have the option of supplying the input reference voltage (VREF) through an external voltage source or by using internal VREF.
For 7 series MIG DDR3 designs, are there guidelines for when internal VREF or external VREF should be used?
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For DDR3 SDRAM interfaces running at or below 800 Mb/s (400 MHz), users have the option of selecting Internal VREF to save two I/O pins or using external VREF. VREF is required for banks containing DDR3 interface input pins (DQ/DQS).
The 7 Series MIG tool includes an Internal VREF option on the FPGA Options screen. Selecting this option properly sets up the UCF constraint to enable Internal Vref.
Note: VREF is required for inputs only. Therefore, if a MIG pin-out includes a bank with outputs only, that is, Address/Control Groups, the VREF pins can be used for Address/Control signals or GPIO (regardless of internal and external VREF selection).
For External VREF specifications, see the appropriate 7 Series FPGA DC and Switching Characteristics Data Sheet:
For general VREF, Internal VREF and DCI information, see the 7 Series FPGA SelectIO Resources User Guide (UG471).