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AR# 42190

Aurora 64b/66b - Soft errors after reset de-assertion

Description

When the Aurora 64B66B core is reset, soft errors are observed after the reset is de-asserted. The Aurora 64B66B core uses the in-built FIFO in the FPGA to implement the Clock Correction and Channel Bonding functionality. All the related controls for the in-built FIFO, such as RD/WR enables andreset, are generated by the core.

When the core is reset during normal operation, the in-built FIFO does not clear its current data contents. This data is latched on its DO port and passed on to the Aurora core. Hence, after reset is de-asserted the Aurora 64B66B core decodes the latched data from the FIFOand reports soft errors.

Solution

The fix for this issue is as follows:

In <user_component_name>_cbcc_gtx_6466.v[hd] file add a register called 'hold_reg', insert the following code:

always @(posedge RD_CLK)
begin
if(RESET)
hold_reg <= 'DLY 1'b0;
else if (do_rd_en)
hold_reg <= 'DLY 1'b1;
end

Replace

assign CC_RX_HEADER_OUT = fifo_dout_i[65:64];
assign CC_RX_DATA_OUT = fifo_dout_i[63:0];

with

assign CC_RX_HEADER_OUT = ( hold_reg == 0 ) ? 2'b00 : fifo_dout_i[65:64]; // To clear the Header bits
assign CC_RX_DATA_OUT = ( hold_reg == 0 ) ? 16'h0 : fifo_dout_i[63:0]; // To clear Data
AR# 42190
Date Created 05/18/2011
Last Updated 02/07/2013
Status Active
Type General Article
IP
  • Aurora 64B/66B