We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42244

13.2 System Generator for DSP - Outputs greater than 52 bits appear to be incorrect


A System Generator design containing outputs greater than 52 bits appear to be incorrect. The problem is seen when checking the outputs in the Matlab/Simulink environment after the output goes through a Gateway Out block. What is causing this?


When a Gateway Out block is used in a Sysgen design, the Fixed Point data will be converted into Floating Point Double data in the Simulink environment. The fractional portion of a Floating Point Double has a range of 52 bits. Therefore, if any output greater than 52 bits is converted using a Gateway Out block, data mismatches can occur.The fixed point data can be monitored internally in the Sysgen design using the WaveScope tool, which is part of the Sysgen Blockset.

If a design requires outputs that are greater than 53 bits, one possible work-around is to split the output into an upper and lower bus, then use two separate Gateway Outs each less than 53 bits. The two busses can then be combined in the Simulink environment using scaling and Data Type Conversion blocks. The Double floating Point Data can be converted into Fixed Point using the Data Type Conversion blocks, then the upper bus can be scaled by a power oftwo and added to the lower bus to perform a concatenation. This method requires the Simulink Fixed Point Blockset.
AR# 42244
Date 01/28/2013
Status Active
Type General Article
  • System Generator for DSP - 13.1
Page Bookmarked