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AR# 42254

FPGA-DSP Slice - Why am I not able to meet the MAX speed listed in the Datasheet when cascading multiple DSPs?

Description

Why am I not able to meet the MAX speed listed in the Datasheet when cascading multiple DSPs?

Solution

The MAX speed numbers listed in the datasheet are for independent DSP Slices.

In some cases, when cascading multiple DSP Slices, these numbers cannot be met due to clock tree skew.

Specific examples:

  • In Virtex-6 -1L, this usually happens when crossing the horizontal break between clock regions. In some cases, you can work around this by locking the DSP column closer to the center of the device.
  • In Spartan-6 -2 and -3, parts usually see this when creating large cascades. There were some improvements to the timing numbers in 13.2, and some designs with long cascades of the DSP48A1 are more likely to be able to meet the specified MAX frequency using the newer software.
AR# 42254
Date Created 05/20/2011
Last Updated 11/27/2013
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-6 CXT
  • More
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Artix-7
  • Kintex-7
  • Spartan-3A DSP
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • Virtex-4 SX
  • Virtex-4Q
  • Virtex-4QV
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Virtex-6QL
  • Virtex-7
  • Virtex-7 HT
  • Zynq-7000
  • Less