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AR# 42290

SysGen 13.2 - DDS Compiler has data mismatches when generated with "Expose Clock Ports" option

Description

A System Generator design that contains the DDS Compiler block using the "Expose Clock Ports" option can have data mismatches when the design is generated and simulated using an HDL simulator.

Solution

This is a known issue with the DDS Compiler. The problem does not occur if the core is reset at the beginning of operation. Therefore, when using the "Expose Clock Ports" option, there is a requirement to assert a reset at the beginning of operation. If the "Clock Enables" option is used instead, the core runs without problem.
AR# 42290
Date Created 05/24/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • System Generator for DSP - 12.1
  • System Generator for DSP - 12.2
  • System Generator for DSP - 12.3
  • More
  • System Generator for DSP - 12.4
  • System Generator for DSP - 13
  • System Generator for DSP - 13.1
  • Less
IP
  • DDS Compiler