AR# 42309


MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center - Design Assistant - Postponing and Pulling-in REFRESH command


The DDR3 JEDEC specification requires refresh cycles at an average periodic interval of tREFI, but to allow improved efficiency up to 8 refresh commands can be postponed or pulled-in to delay or reduce the number of refresh commands sent later. For more information on postponing and pulling-in refresh commands, refer to the DDR3 JEDEC specifications.

Note: This Answer Record is part of the Xilinx MIG Solution Center(Xilinx Answer 34243) Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


MIG supports the pulled-in refresh feature of DDR3 for Virtex-6 and 7 series FPGA designs, and generates up to 8 pulled-in refresh commands when the rank is not busy. When the rank is active, the refresh commands are sent on their periodic cycles as defined by the tREFI interval. Pulling-in refresh commands when the RANK is not active improves bus efficiency during normal operation.

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Answer Number Answer Title Version Found Version Resolved
34371 MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center - Design Assistant - Auto-Refresh Counter (Refresh Period) N/A N/A
AR# 42309
Date 09/18/2012
Status Active
Type Solution Center
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