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AR# 42330

13.1 - VHDL design and Verilog testbench causes EXCEPTION_ACCESS_VIOLATION crash


My project successfully synthesizes and implements, but fails with the following "EXCEPTION_ACCESS_VIOLATION" error when running a Behavioral Simulation:

"Compiling module gtx5f_408568
Compiling module GTX_DUAL_FAST(2000,1000)
Compiling module TOP_TRX_MULTI_LINKS_TB
ERROR:Simulator:754 - Signal EXCEPTION_ACCESS_VIOLATION received

Process "Simulate Behavioral Model" failed"


This error can occur when using a Verilog Testbench with a design written in VHDL, and VHDL type hierarchical boundary references are used in the Verilog testbench. 

An example of this is below:

assign RefClk = uut.RefClk;

In this example, RefClk is within the UUT instance of the VHDL file, but is not an output port.

The problem occurs because Verilog does not have the ability to access signals in lower levels of hierarchy.

To work around the problem in this case, bring any signals out from the test files to the testbench via ports.

AR# 42330
Date 10/24/2014
Status Active
Type General Article
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3