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AR# 42339

Spartan-6 FPGA Integrated Block for PCI Express - What is the PMA_RX_CFG setting for an asychronous link?

Description

Version Found: 1.1; v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 45702).

What is the best setting for the GTP attributePMA_RX_CFG for an asynchronous link?

Solution

For asynchronous links, meaning that each link partner is clocked by a different oscillator, the recommended value for PMA_RX_CFG is 25'h05CE049. Set this value in the file called gtpa1_dual_tile_wrapper.v[hd] in the generated core's source directory.For more information regarding clocking and PCI Express, see (Xilinx Answer 18329).

Revision History
01/18/2012 - Updated; added reference to 45072
07/06/2011 - Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42569 Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45702 Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions N/A N/A
AR# 42339
Date Created 07/06/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )