AR# 42343

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13.2 PlanAhead - DRC error regarding IDELAYCTRL

Description

When more than oneIDELAYCTRL exists with IODELAY_GROUP attributes, PlanAhead software gives the following DRC error.

IDLVCTRL #1 Error
Design has more than one IDelay controllers unloced (for example delayctrl1 and delayctrl2). At most one of them can be unloced.

Example code:

(* IODELAY_GROUP = "aa" *)
IDELAYE2
# (
.CINVCTRL_SEL ("FALSE"), // TRUE, FALSE
.DELAY_SRC ("IDATAIN"), // IDATAIN, DATAIN
.HIGH_PERFORMANCE_MODE ("FALSE"), // TRUE, FALSE
.IDELAY_TYPE ("FIXED"), // FIXED, VARIABLE, or VAR_LOADABLE
.IDELAY_VALUE (20), // 0 to 31
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA")) // CLOCK, DATA
idelaye2_inst_aa
(
.DATAOUT (data_o_aa),
.DATAIN (1'b0), // Data from FPGA logic
.C (1'b0),
.CE (1'b0),
.INC (1'b0),
.IDATAIN (data_aa), // Driven by IOB
.LD (1'b0),
.LDPIPEEN (1'b0),
.REGRST (1'b0),
.CNTVALUEIN (5'b00000),
.CNTVALUEOUT (),
.CINVCTRL (1'b0)
);

(* IODELAY_GROUP = "bb" *)
IDELAYE2
# (
.CINVCTRL_SEL ("FALSE"), // TRUE, FALSE
.DELAY_SRC ("IDATAIN"), // IDATAIN, DATAIN
.HIGH_PERFORMANCE_MODE ("FALSE"), // TRUE, FALSE
.IDELAY_TYPE ("FIXED"), // FIXED, VARIABLE, or VAR_LOADABLE
.IDELAY_VALUE (20), // 0 to 31
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA")) // CLOCK, DATA
idelaye2_inst_bb
(
.DATAOUT (data_o_bb),
.DATAIN (1'b0), // Data from FPGA logic
.C (1'b0),
.CE (1'b0),
.INC (1'b0),
.IDATAIN (data_bb), // Driven by IOB
.LD (1'b0),
.LDPIPEEN (1'b0),
.REGRST (1'b0),
.CNTVALUEIN (5'b00000),
.CNTVALUEOUT (),
.CINVCTRL (1'b0)
);

(* IODELAY_GROUP = "aa" *) IDELAYCTRL
delayctrl1 (
.RDY (),
.REFCLK (REF_CLOCK),
.RST (IO_RESET));

(* IODELAY_GROUP = "bb" *) IDELAYCTRL
delayctrl2 (
.RDY (),
.REFCLK (REF_CLOCK),
.RST (IO_RESET));

However, implementation can complete successfully.

Solution

PlanAhead tool DRC should be aware of this valid usage of multiple IDELAYCTRLs.

The constraint IODELAY_GROUPgroups a set of IDELAY and IODELAYs with an IDELAYCTRL and enables automatic replication and placement of IDELAYCTRL in a design. In this case, locking each IDELAYCTRL instance down is unnecessary.

This DRC error should be ignored for 7 series designs.

AR# 42343
Date 05/19/2012
Status Archive
Type Known Issues
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