This document describes techniques to debug link training issues related to designs using the Virtex-5 FPGA Endpoint Block Plus core for PCI Express. A complete list of signals to capture in ChipScope Pro when debugging link training issue has been provided. ChipScope Pro screen captures illustrate how to analyze those signals and establish theories on potential reasons causing the problem.
There are two major sections in this guide. The first section provides an overview of link training including the LTSSM states and TS1 and TS2 ordered sets. The second section focuses on using ChipScope Pro to capture the relevant signals on the GTP/GTX interface to identify potential problems during link training. This guide helps the user understand how the LTSSM progresses and what states the signals should be in during this progression. This debugging guide concludes with a checklist of common problems to address when experiencing link training issues.
There are usually three major link training failures. One is a complete failure to establish a link of any width; indicated by the core output trn_lnk_up_n not asserting. The second is when the link trains to a lower width than intended, such as an x8 link training as x4. Third, is a link that is constantly entering into the RECOVERY state. Link training problems are normally due to board signal integrity problems or improper GTP/GTX usage. The board must meet both the electrical requirements set forth by the GTP/GTX user guides and also the PCI Express Base Specification.
07/19/2011 - Initial Release