We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42436

MIG 7 Series - What capture clock is being used for DQ byte groups in the 7 Series?


The 7 Series MIG controllerusesa capture clock that is phase aligned to read DQS in the PHASER_IN phase locked stage to capture the DQ signals for a byte group. The calibration logic makes use of the fine delay increments available through the PHASER to ensure thecapture clock is centered inside the read data window, ensuring maximum data capture margin.


The 7 Series memory controllercore usesthePHASER_IN hard block to adjust delay shift for the DQ capture clock for each byte lane during Read Leveling.The phase shiftis called thefine phase delay and the resolution is 1/64 of data period. Therefore, the resolution will change when the memory clock period changes.
AR# 42436
Date 02/22/2013
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG
Page Bookmarked