AR# 42475


13.1 PlanAhead - DIFF_HSTL_I_DCI outputs missing rule/data to catch illegal placement in HR bank


Why are DIFF_HSTL_I_DCI outputs in 7 series FPGAs not getting a DRC error when assigned in an HR bank?


PlanAhead tool should generate an error stating that the particular DCI standard is not allowed in this particular bank.

This is a known issue and fixed in PlanAhead tool 13.2.
AR# 42475
Date 07/11/2011
Status Active
Type Known Issues
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