For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:
For Spartan-6 FPGAs, the options for correction by replace and error classification are not supported in this release when using ISE Design Suite13.2. The BitGen softwarein the ISE Design Suite13.2 does not produce the needed essential bit files to perform these options. This should be added to BitGen in ISE Design Suite13.3.
The Soft Error Mitigation Controller is not impacted by the Spartan-6 9K BRAM issues. See (Xilinx Answer 41955) for more information.
- ISE 13.2 software support.
- Added support for QVirtex-6 Lower Power devices.
- Added support for all Spartan-6 devices.
The following device families are supported by the core for this release.
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XC LXT/SXT
Virtex-6 -1L XQ LXT/SXT
Spartan-6 XC LX/LXT
Spartan-6 XA LX/LXT
Spartan-6 XQ LX/LXT
Spartan-6 -1L XC LX
Spartan-6 -1L XQ LX
(Xilinx Answer 43106) - Soft Error Mitigation Controller v2.1 - External Shim interfacing with SPI device issues the "enable 32-bit addressing" multiple times at startup
(Xilinx Answer 39350) - Soft Error Mitigation Controller- Timing Simulation Error: Warning: /X_FF RECOVERY Low VIOLATION ON RST WITH RESPECT TO CLK
(Xilinx Answer 40991) - Soft Error Mitigation Controller - Correction by Replace not supported with EasyPath Devices
(Xilinx Answer 42482) - Soft Error Mitigation Controller v2.1 - Hold time violations in par and trce when targeting Virtex-6 LX760 -1L
(Xilinx Answer 42494) - Soft Error Mitigation Controller v2.1 - Correction by Replace and Classification features are not supported in Spartan-6
(Xilinx Answer 42483) - Soft Error Mitigation Controller v2.1 Component switching limit errors when targeting Spartan-6 devices
(Xilinx Answer 42997) - Soft Error Mitigation Controller v2.1 - Mistake in User Guide regarding address pointers to replacement and classification data
07/13/2010 - Addded 43106
07/06/2011 - Initial Release