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AR# 42574

SPI-4.2 v10.5 - Timing failures occasionally seen when using Dynamic Phase Alignment (DPA)


In the SPI-4.2 v10.5 core, occasionally timing failures have been seen in the Sink core when using Dynamic Phase Alignment (DPA).


Timing failures can often be avoided by changing the cost table or turning on extra effort in MAP and PAR.  If failures are encountered, please contact Xilinx technical support to explore the issue further.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42572 SPI-4.2 v10.5 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
AR# 42574
Date 05/26/2014
Status Archive
Type General Article
  • SPI-4 Phase 2 Interface Solutions
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