Description

This Answer Record contains the Release Notes for the Aurora 8B/10B v5.1 Core, released in ISE Design Suite 11.2, and includes the following:

• General Information
• New Features
• Bug Fixes
• Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.

Solution

• ISE 12.2 software support
• Addition of Use ChipScope Pro Analyzer checkbox in GUI to include ChipScope cores as part of example design
• Virtex-6 LXT/SXT/HXT line rate increased from 6.5 Gbps to 6.6 Gbps
• Virtex-6 CXT -1 speed grade device line rate increased from 3.125 Gbps to 3.75 Gbps
• Virtex-6 HXT (GTX transceivers) support
• Virtex-5 Qpro devices support
• Virtex-6 Qpro devices support
• Spartan-6 Qpro devices support
• Automotive Spartan-6 devices support

• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Spartan-6 XC LXT
• Spartan-6 XA
• Spartan-6 XQ LXT
• Virtex-5 XC LXT/SXT/FXT/TXT
• Virtex-5 XQ LXT/SXT/FXT

• Virtex-6 Aurora: default value for TXDIFFCTRL is too low. Core uses 4'b0000 as default value and it changed to 4'b1000.
  Refer to UG366 for more details on TXDIFFCTRL values.
  CR number 561723
• Update Spartan-6 PMA_RX_CFG settings based on latest characterization data PMA_RX_CFG attribute updated for Spartan-6.
  CR number 563542
• Updated the min PLL range from 1.5 to 1.48 for Virtex-5/Virtex-5Q GTX. CR number 560012 This update is from latest DS202 (v5.3)
• Generating Aurora 8B10B v5.1 for S6 with line rate 3.125/refclk 78.13 gives unknown error.
  CR number 555870
• Change the "CLK_COR_SEQ_1_1_0/1" attribute from 10'b0000000000 to 10'b0100000000 when clock correction is disabled.
  CR number 555432
• Spartan-6 Aurora 8b/10b v5.1 instantiates IBUFDS_GTXE1.
  CR number 555780
• Simplex RX should also have timer option enabled in the GUI.
  CR number 523323
• Update default setting for PMA_COM_CFG_WEST[13:12] attribute for production silicon.
  CR number 558556
• PMA_COM_CFG_WEST[13:12] got updated to 2'b10.
• The value of CHAN_BOND_LEVEL_0 and CHAN_BOND_LEVEL_1 parameters is incorrectly set.
  CR number 538515 CHAN_BOND_LEVEL_0 and CHAN_BOND_LEVEL_1 parameters were set in hexadecimal. These are updated as integers as per UG198.
• Fixed min line rate for Virtex-6 and Virtex-6 low power family.
• Virtex-6 CXT devices have 0.675 Gb/s as min line rate. Virtex-6 LXT/SXT/HXT and Virtex-6 -1L LXT/SXT has 0.6 Gb/s as min line rate.
  CR number 559154
• Fixed misleading license warning message during core generation.
• Aurora 8B10B core is made as free IP core and doesn't require any license for core generation.
  CR number 536603
• Removed -t switch from the par command in the implementation scripts. CR number 551312Update MMCM VCO frequncy range from 400MHz to 600MHz.
  CR number 543847
• De-feature GTX PLL feedback divider /1 for Virtex-6 & Virtex-6 -1L family production silicon.
  CR number 544243
• Update charge pump attributes for Virtex-6 & Virtex-6 -1L family GTX.
  CR number 544242
• Appendix D of UG353 does not match up with RocketIO GTP Wizard Selection Step 3.
  CR number 550641
• Appendix D of UG353 explains the procedure for Virtex-5 GTP/GTX. This procedure does not hold true for other transceiver wizards like Virtex-6 GTX or Spartan-6. Appendix D has been rewritten completely for each of the wizard wrapper generations.