Customers using the ISE13.1 software should be aware that the port list in 7 Series FPGAs Transceivers wizard v1.4 and model (released with ISE 13.2 software) has been modified, and users need to update their instantiations to account for these port changes.
Port Name Changes
'CPLL_RXOUT_DIV' is changed to'RXOUT_DIV'
'CPLL_TXOUT_DIV' is changed to 'TXOUT_DIV'
These names are changed to reflect the fact that these output dividers in the channel can be used with either QPLL or CPLL. These names have been updatedin v1.2of the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476).
'BGBYPASS' is changed to'BGBYPASSB'
'BGMONITOREN' is changed to 'BGMONITORENB'
For example, these ports in the GTXE2_COMMON moduledefined in the gtwizard_v1_x.v/vhd file are being changed as follows:
BGBYPASSB => tied_to_vcc_i,
These new port names will be used going forward starting from ISE 13.2 software.
Please see the following Answer Records forthe impact of these port changes on specific protocol IPs:
PCI-Express:see(Xilinx Answer 42838)
CPRI:see(Xilinx Answer 42626)
OBSAI:see(Xilinx Answer 42627)
Ethernet 1000BASE-X PCS/PMA or SGMII:see(Xilinx Answer 42672)
XAUI:see(Xilinx Answer 42673)
RXAUI:see(Xilinx Answer 42674)
Ten Gigabit Ethernet PCS/PMA: see (Xilinx Answer 42675)