I am trying to simulate the negotiation of the line speed between two CPRI cores. In the CPRI specification v4.1 in Sec. 184.108.40.206 "State B - L1 Synchronization and Rate Negotiation," it describes that the master changes its line speed every T1 = 0.9-1.1s and the slave every T1' = 3.9-4.1s.
For simulation, these are very long periods. Is there is a way to shorten these periods for CPRI core simulation?
The auto-negotiation times in the built core cannot be shortened. If you have a source code license, you can set C_SPEEDUP_SPEEDNEG to true in the instantiation of the link_manager in cpri_gen.vhd.
If not, you can still use the example design loopback testbench to test the operation at different speeds. You can use the write_speed_capability function to change the speed at the start of the simulation. You should then see the looped back link coming up at different speeds.
For LogiCORE CPRI Release Notes and Known Issues, see (Xilinx Answer 36969).