To manage this issue, there are two changes required to the GTXE2 modules.
Note: These changes only apply to cores that select 9.830 Gbps.
1. Go to the v7_gtwizard.vhd file in the example_design/gtx_and_clocks/gtx directory.
2. Change the following lines in the v7_gtwizard.vhd file:
BGBYPASSB => tied_to_vcc_i,
Note: These changes apply to cores that select any line rate.
1. Go to the v7_gtwizard_gt.vhd file in the example_design/gtx_and_clocks/gtx directory.
2. Change the following lines in the v7_gtwizard_gt.vhd file:
For Release Notes and Known Issues for the LogiCORE CPRI, please see (Xilinx Answer 36969).