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AR# 42630

Spartan-6 - BUFPLL LOCK signal does not assert when DIVIDE=1


When using a BUFPLL with the DIVIDE set to 1, the LOCK signal from the BUFPLL never asserts, why?


Using a DIVIDE setting of 1 was never identified as a valid use-case for the BUFPLL, as the BUFPLLtypically onlydrives the ISERDES/OSERDES blocks with bit-widths of 2-8.Though in the ISE software revision 14.3 and earlier software the default value for DIVIDE was 1, the only recommended values are 2-8. For unusual designs that require DIVIDE = 1,it can still be used, but the LOCK output signal will not assert correctly - and thereforethe LOCK pin should notbeconnected to anythingin the design. Starting in Xilinx's ISE software revision 14.4, there will be a Design Rule Check (DRC) Error if the BUFPLLs DIVIDE value is set to 1 and the LOCK output is connected to other logic in the design.
AR# 42630
Date 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
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