AR# 42665

MIG 7 Series - Why does the MIG Example Design fail in BitGen?

Description

When I generate a bitstream for a MIG 7 Series Example Design, the following error message occurs:

"ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD).This maycause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected.To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -g UnconstrainedPins:Allow."

Solution

This error message occurs when generating the bitstream for the MIG 7 Series Example Design when one or all of the system and status signals internally. If any of the pins are left as "No connect", the ISE tools select the pins as needed in the implementation phase.

For more information about the error message and how to downgrade this to a warning message, please refer to(Xilinx Answer 41615).

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
46227	MIG 7 Series Solution Center - Top Issues	N/A	N/A

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
41227	MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2	N/A	N/A
41615	7 Series, BitGen (13.2 and later) - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"	N/A	N/A

AR# 42665
Date	12/15/2012
Status	Active
Type	General Article
Devices	Artix-7 Kintex-7 Virtex-7 Virtex-7 HT
IP	MIG 7 Series

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