NOTE: If you use PlanAhead tool to define the P-side LOC and IOSTANDARD constraints, the tool will automatically write the N-side LOC and IOSTANDARD constraints.
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
42757 | Virtex-7, Kintex-7, 13.2, 13.3 - GTX IBERT-"ERROR:Bitgen:342" Occurs During Bitstream Generation of GTX IBERT core | N/A | N/A |
41227 | MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 | N/A | N/A |
41615 | 7 Series, BitGen (13.2 and later) - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" | N/A | N/A |