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  3. AR# 42678: 13.2 Bitgen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"

AR# 42678

13.2 Bitgen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"

Description

For the 7 Series family, bitgen will issue an error message if there are any I/Os that do not have pin constraints or have an undefined I/O Standard. See Xilinx (Xilinx Answer 41615) for further details.

This error message erroneously occurs when there is a differential pair and the P-side has a LOC and IOSTANDARD constraint.

Solution

This is a bug in software and will be fixed in a future software version. To work around, the user can define the LOC and IOSTANDARD for the N-side of the differential pair.

NOTE: If you use PlanAhead tool to define the P-side LOC and IOSTANDARD constraints, the tool will automatically write the N-side LOC and IOSTANDARD constraints.


Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
42757 Virtex-7, Kintex-7, 13.2, 13.3 - GTX IBERT-"ERROR:Bitgen:342" Occurs During Bitstream Generation of GTX IBERT core N/A N/A
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
41615 7 Series, BitGen (13.2 and later) - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" N/A N/A
AR# 42678
Date 12/15/2012
Status Active
Type General Article
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