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AR# 42690: 13.1 Timing - Block RAM in a Spartan-6 device in SDP mode includes invalid timing path
13.1 Timing - Block RAM in a Spartan-6 device in SDP mode includes invalid timing path
In SDP mode on a Spartan-6 device block RAM, both input ports are clocked on CLKA and both output ports are clocked on CLKB. However, TRCE reports timing paths from CLKA (write clock) on the output ports to the other synchronous components.
The issue is scheduled to be fixed in O.61xd.
To work around this issue, add constraints to ignore the path which should not be analyzed.
NET "clk_wr" TNM = RAMS "BRAM_WR"; TIMESPEC TS_BRAM_WR_FF = FROM "BRAM_WR" TO "FFS" TIG;