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AR# 42715

FIFO Generator v8.2 - Release Notes and Known Issues for ISE Design Suite 13.2

Description

This Release Notes and Known Issues Answer Record is for the FIFO Generator v8.2 Core, released in the 13.2 ISE Design Suite software and contains the following information:

  • General Information
  • New Features
  • Bug Fixes
  • Known Issues
  • Technical Support

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025) at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.

Solution

General Information

For the most recent updates to the IP installation instructions for this core, please go to: 
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm.

For system requirements, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm.

This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v8.2 solution. For the latest core updates, see the product page at: http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm.

New Features in v8.2 

  • ISE 13.2 software support
  • Kintex-7L, Virtex-7L, Artix-7, and Zynq device support

Bug Fixes in v8.2

The following issue is resolved in v8.2:

  • The FIFO Generator core and the behavioral models in AXI Streaming mode accept the data during reset (s_aresetn is low).

Known Issues in v8.2

The following are known issues for v8.2:

  • In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration) into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
  • M_ACLK mapping for the write response and read data channel is incorrect. M_ACLK is mapped to the read side rather than the write (CR617397).

Technical Support

To obtain technical support, create a WebCase. Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

Linked Answer Records

Associated Answer Records

AR# 42715
Date Created 07/05/2011
Last Updated 05/23/2014
Status Archive
Type Release Notes
Tools
  • ISE Design Suite - 13.2
IP
  • FIFO Generator