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AR# 4272

SYNPLIFY 5.x - Bus notation differs across XNF, EDIF, and UCF

Description

Urgency: Hot

General Description:

In Synplify 5.0, users must keep in mind the bus notation syntax when using EDIF, XNF, or UCF.

Please see (Xilinx Answer 2649) on information on modifying the bus notation in an EDIF generated netlist.

Solution

In Synplify 5.x, users must keep in mind the bus notation syntax when using EDIF, XNF, or UCF.

The EDIF format differs in bus notation from the XNF output file previously generated in versions 3.0 and below.

+-------+-------+-------+-------------------------------------------+

| Ver. | 3.x | 5.x | Comments |

+-------+-------+-------+-------------------------------------------+

| XNF | B | B | Buss signals expanded |

+-------+-------+-------+-------------------------------------------+

| EDIF | X | B(I) | See Note 1; Not using "syn_noarrayports" |

+-------+-------+-------+-------------------------------------------+

| EDIF | X | B[I] | See Note 1; Using "syn_noarrayports" |

+-------+-------+-------+-------------------------------------------+

NOTE 1:

Synplify 3.x does not produce EDIF. However, Synplify 5.x has the option of producing EDIF.

Consider the EDIF snippet from Synplify 5.x:

(port (array (rename tenthsout "TENTHSOUT[9:0]") 10) (direction OUTPUT))

Alliance 1.4

------------

EDIF2NGD 1.4 does not handle embedded ranged strings in array names appropriately. See (Xilinx Answer 4891) for details. The signal, "TENTHSOUT[9:0]", is recognized as a 1-bit wide instead of a vector.

The user can specify to have their bus ports expanded to bits with the "syn_noarrayports" attribute within Synplify. Please see (Xilinx Answer 504). Also, within COREGen or LogiBlox, select the bus notation as "[]". Please read (Xilinx Answer 4041) for a description of generating COREGen modules.

Alliance 1.5i

------------

EDIF2NGD 1.5i expands an array construct. It *always* uses parenthesis. The delimiters used in the range part of the array name have no effect on the actual expansion. See (Xilinx Answer 5416) for details. Within COREgen or LogiBlox, select the bus notation as "()". Please read (Xilinx Answer 4041) for a description of generating COREGen modules.

If you are using the "syn_noarrayports" attribute within Synplify, then please select the bus notation as "[]".

AR# 4272
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article