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AR# 42742

LogiCORE FIR Compiler v5.0 - Why is the RDY Signal Remaining HIGH When Asserted?


In my FIR Compiler design, the RDY signal remains HIGH when asserted.


This issue occurs when the hardware over-sampling rate is used. If the input rate is higher than the output rate, the output data isalways valid. To get the correct data rate, use the sample rate in place of the over-sampling rate and the RDY toggles at the output data rate.
AR# 42742
Date 12/15/2012
Status Active
Type General Article
  • FIR Compiler
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