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AR# 42760

Endpoint Block Plus Wrapper v1.15 for PCI Express - Release Notes and Known Issues for ISE Design Suite 13.2

Description

This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.15, released in ISE Design Suite 13.2, and contains the following information:
  • General Information
  • New Features
  • Bug Fixes

Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025):
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features

  • ISE 13.2 software support
  • Dual Core feature support removed

Supported Devices

  • Virtex-5 XC LXT/SXT/TXT/FXT
  • Virtex-5 XQ LXT/SXT/FXT

Resolved Issues

  • Support for Dual Core Design Example
    • CR 540444
    • Support for Dual Core Example Design has been removed on the FX70T device.
  • Incoming Memory Reads Re-ordered
    • CR 582981
    • Issue resolved where Memory Reads in the Endpoint Receive direction were re-ordered, when trn_rnp_ok_n is also deasserted.
  • Transmit TLPs allowed intBuffer before it is empty
    • CR 583039
    • Issue resolved where the Core, in the Transmit direction) accepted TLPs on the Transaction Interface buffer, before the Buffer is completely empty.
  • Packets with same ACK/NAK sequence number get lost
    • CR 539017
    • Issue resolved where an 8b/10b error on the link causes the incoming packet to be lost.
  • Finite Completions setting in GUI working
    • CR 588027
    • Issue resolved where the Finite Completions setting in the GUI was not getting translated on the design itself
  • UpConfigure Fix
    • CR 592181
    • Issue resolved where the Upconfigure Fix was causing the Lane to hold an incorrect value when the lanes are unaligned.

Known Issues

There are three main components to the Endpoint Block Plus Wrapper for PCI Express:

  • Virtex-5 FPGA Integrated Block for PCI Express
  • Virtex-5 FPGA GTP/GTX Transceivers
  • Block Plus Wrapper FPGA fabric logic

The known issues for the integrated block and GTP/GTX transceivers are found in the LogiCORE IP Endpoint Block Plus v1.14 for PCI Express User Guide (UG341) delivered with the core and found at:
http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express_v5pciexpressblockplus.htm

(Xilinx Answer 34706) - Endpoint Block Plus Wrapper v1.15 for PCI Express - Disconnecting Packets on TX Interface when Interfacing with a link Partner Advertising Non-Infinite Completion Credits Can Eventually Stall the Transmit Interface
(Xilinx Answer 51600) - Endpoint Block Plus Wrapper v1.15 for PCI Express - Example Design Simulation Fails for x8 Configuration

Revision History
09/03/2012 - Added (Xilinx Answer 51600)
07/06/2011 - Initial release

AR# 42760
Date Created 06/23/2011
Last Updated 09/04/2012
Status Active
Type Release Notes
Devices
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
Tools
  • ISE Design Suite - 13.2
IP
  • Endpoint Block Plus Wrapper for PCI Express