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AR# 42777

13.1 Project Navigator - Synthesis or Simulation fails with "Failed to Regenerate Core"


In Project Navigator, I run a simulation, synthesis, or implementation process and the following error appears in the console window.

Failed to Regenerate Core

The process does not continue and even persists if I select all cores in my design and regenerate them successfully.


This issue has been seen with cores that can only generate one HDL language (e.g. later versions of MIG) and some networking cores which produce example designs (e.g. PCIe).

The error message is not really accurate. What is happening is that Project Navigator runs a process to determine if the core needs to be regenerated. In this process, it evaluates the files delivered with the IP core to determine if it can find all the files that will be needed. If there are missing files, the process fails.

In the case of the MIG core, this issue can be worked around by changing the intermediate HDL language (Select the core in Project Navigator then right click on "View HDL Functional Model" and select Process Properties).

Another way to work around the problem is to remove the .xco file from the project and add the top level wrapper for the core and all associated netlists.

This issue has been resolved in ISE Design Suite 13.2

AR# 42777
Date 05/19/2012
Status Archive
Type Known Issues
  • ISE Design Suite - 13.1
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