AR# 4278: M1.4 PAR - FPGA Express 2.1.1 designs with incomplete RLOC specifications fail in PAR.
M1.4 PAR - FPGA Express 2.1.1 designs with incomplete RLOC specifications fail in PAR.
Cases have been seen where FPGA Express 2.1.1 creates loadable counters that only have the first and last registers RLOC'd. As a result the M1 mapper creates an RPM macro that contains only the first and last CLBs of the carry chain. The rest of the counter logic is mapped into individual CLBs. PAR is unable to handle placement of a carry chain that is a mixture of a macro and independent CLBs and fails with the error:
ERROR:x4kpl - RPM "inc_rpl_8_9_2" contains a partial carry logic chain. This is not supported in the current release. Carry logic chains must either be fully contained in the RPM or not in an RPM at all. The carry logic chain is broken at CLB "N138" and is driven by CLB "N93" which is not contained in this RPM.
This problem can be worked around by either completing the RLOC specifications for the middle registers in the .ucf file (1) or by canceling the RLOC specifications for the end registers in the .ucf file (2). PAR will successfully place the carry chain either way.
(1) The following constraints fix a counter that already has INST QOUT_reg<0> and INST QOUT_reg<7> RLOC'd by FPGA Express: