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AR# 42803

Aurora 64b/66b - BitGen Errors in the 13.2 ISE Software

Description

When I generate a bitstream for an Aurora 64b/66b 7 series design in the 13.2 ISE software, the following error message occurs:

"ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -g UnconstrainedPins:Allow."

Solution

This error message occurs when generating the bitstream for the Aurora 64b/66b example design for the 7 series in the 13.2 ISE software. The message is regarding the following pins:

  • DATA_ERR_COUNT[7:0]
  • CHANNEL_UP
  • PMA_INIT
  • INIT_CLK
  • RESET
  • LANE_UP
  • HARD_ERR
  • SOFT_ERR

For more information about the error message and how to downgrade this to a warning message, please refer to (Xilinx Answer 41615).

Linked Answer Records

Associated Answer Records

AR# 42803
Date Created 07/12/2011
Last Updated 02/06/2013
Status Active
Type Known Issues
IP
  • Aurora 64B/66B