2. Support
  3. AR# 4281: Foundation F1.5: Changing Synthesis Options gives ambiguous "force updated" message
  4. AR# 42811: MIG 7 Series v1.2 v1.3 - Setup error on PHY hard blocks due to incorrect timing model

AR# 42811

MIG 7 Series v1.2 v1.3 - Setup error on PHY hard blocks due to incorrect timing model

Description

In the ISE 13.2 and 13.3 software release, an error in the timing model for the PHASER and the PLL can cause incorrect setup time errors on paths that start at a PHY hard block and end at a PHY hard block.

Solution

The example below shows a possible setup time violation in MIG 7 Series 1.2. 

This path starts with CLKOUT2 (which is the sync_pulse) and ends at generation of MEMREFCLK. 

This is analyzed for one clock period which is 1.25 ns (800 MHz).

Path1
------------------------------------------------------- -------------------
PLLE2_ADV_X1Y8.CLKOUT2 Tpllcko_CLK 0.088 u_mig_7series_v1_2/u_ddr3_infrastructure/plle2_i
u_mig_7series_v1_2/u_ddr3_infrastructure/plle2_i
PHY_CONTROL_X1Y6.SYNCIN net (fanout=22) 1.530 u_mig_7series_v1_2/sync_pulse
PHY_CONTROL_X1Y6.MEMREFCLK Tpctcks_SYN 0.168 u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_2.phy_4lanes/phy_control_i
u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_2.phy_4lanes/phy_control_i
------------------------------------------------------- ---------------------------

Path2
------------------------------------------------------------- -------------------
PHY_CONTROL_X1Y8.PHYCTLEMPTY Tpctcko_EMP 0.576 u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_0.phy_4lanes/phy_control_i
u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_0.phy_4lanes/phy_control_i
PHY_CONTROL_X1Y6.PHYCTLMSTREMPTY net (fanout=3) 0.930 u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_ctl_empty<0>
PHY_CONTROL_X1Y6.MEMREFCLK Tpctckd_EMP 0.034 u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_2.phy_4lanes/phy_control_i
u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_2.phy_4lanes/phy_control_i
------------------------------------------------------------- ---------------------------

 

To resolve the timing errors, locate the following localparam in the 'user_design/rtl/phy_ddr_mc_phy.v' module:

localparam MASTER_PHY_CTL = 0;


  • For customers using 3 banks, change this to a 1.
  • For customers using 1 bank, leave this at 0.
  • For customers using 2 banks, set this to either 0 or 1 depending on whether the address/control bank is located physically above or below the data bank.

This issue is fixed in MIG 7 Series v1.4.
AR# 42811
Date 10/13/2014
Status Active
Type Known Issues
Devices
IP